A brief summary of the numerous possibilities for manufacturing bipolar transistors is contained in the magazine article "Advances in Bipolar VLSI" by George R. Wilson in the Proceedings of the IEEE, Volume 78, No. 11, 1990, pages 1707-1719.
The original p-n-insulated bipolar technology is based on the oxidation of the Silicon surface, the single p-n-insulation of an epitaxial layer and the diffusion of doping substances from gaseous sources.
In spite of many technological advances, this manufacturing technology was used for a very long time and to some extent is still in use today.
Modern bipolar technologies today use new technological steps some of which have been developed for MOS technologies. Some examples are: Ion implantation, plasma etching, local oxidation of Silicon (LOCOS) and the use of polycrystalline Silicon.
Since epitaxial processes are expensive, attempts are made to replace this technological part step by other suitable methods. The solution is production of the collector region (buried collector) by means of ion implantation with high accelerating energy. Such a bipolar process constitutes the latest state of the art and will therefore be described briefly as follows:
In a first process step, the N-wells which are later to contain the transistor structures, are produced in a p-doped semiconductor substrate. In order to achieve good transistor parameters, the doping (number of foreign atoms per cubic centimeter) must be greater in the depth of the N-well than at the semiconductor surface, so that it is necessary to work with very high implanting energy. Several implanting steps must be carried out in order to obtain the desired doping profile. For example, in the first step implantation with Phosphorus ions is carried out to produce a highly doped buried layer (sub-collector) with a maximum doping concentration of 10.sup.18 cm-3 at a depth of approx. 4 .mu.m. Then follow two further implantations in the energy range between 0.6 MeV and 1.8 MeV, producing between the semiconductor surface and the sub-collector a relatively homogeneous doping concentration of 10.sup.16 cm.sup.-3. The three aforementioned implantations are introduced through a single structured masking layer which must be sufficiently thick to really shield off the high energy ions (e.g. 5 .mu.m thick Aluminum). Thereafter the implantation mask is removed and the process steps as known from conventional bipolar or BiCMOS processes are carried out.
In the case of a BiCMOS process one would thereafter define the active regions with the LOCOS process (local oxidation) using a further mask. After this, again using a mask, a base layer is implanted by a p-doping of medium concentration. Two further masking processes introduce a p.sup.+ -doping for the base contact and a n.sup.+ -doping for the emitter.
After depositing an intermediate insulator, contact windows are etched free and a metalization is deposited for establishing the electrical connections for emitter, base and collector.
In spite of the utilization of ion implantation, the effort required for this bipolar process is still very great, because many masking steps are necessary and these steps must be mutually adjusted very accurately. The list of minimum required processing stages (the p.sup.+ -implantation for the base contact can possibly be omitted under certain circumstances) contains at least the following six masking steps:
1) Implantation of the N-Wells PA1 2) Implantation of the base PA1 3) Implantation of the emitter PA1 4) Opening of the contact holes PA1 5) Metalization PA1 6) Passivising
A particular disadvantage of the aforementioned processes which must be pointed out is that the individual masking levels entail certain mutual adjustment tolerances. As a consequence of these adjustment tolerances, there will be corresponding fluctuations of the transistor parameters on a given silicon wafer as well as between different wafers. The adjustment tolerances also lead to more surface area on the wafer occupied by each transistor because the adjustment tolerances must be taken into account in the construction of the transistors and corresponding compensation areas must be provided. The compensation areas introduce enlarged parasitic elements which have a negative effect on the performance of the circuit.